Shaping the Semiconductor Workforce in the Age of AI

Detailed Summary

Speaker	Key Points
Moderator (Paul Triolo)	Introduced the session, thanked the audience, and underscored the convergence of the India AI Mission and the India Semiconductor Mission. Noted the recent signing of the Pax Silica agreement, a pledge for a trusted, geopolitically‑resilient semiconductor supply chain.
Mr. S Krishnan (METI Secretary)	Praised the METI team, invited attendees to explore the extended exhibition (open till 8 p.m.), and set the policy backdrop: the India Semiconductor Mission 2.0 expands focus beyond wafer fabs to the entire ecosystem – design, equipment, manufacturing, and workforce. Highlighted that India’s semiconductor market is projected to hit $100 bn by 2030, demanding a large domestic talent pool and export‑ready capabilities.
Mr. Rangesh Raghavan (Lam Research)	Briefly mentioned Lam’s 25‑year presence in India, its Bengaluru systems‑engineering lab, and the company’s commitment to integrating Indian supply chains with global operations. Emphasised the urgency of advanced‑manufacturing skills – not just design or AI, but precision equipment fabrication.
Minister Shri Ashwini Vaishnaw (arrived later)	Acknowledged the Minister’s past contributions to the sector and welcomed his presence (no direct remarks captured in the transcript).

2. David Fried’s Keynote – “Semiverse: Building the Workforce for an AI‑Powered Semiconductor Future”

2.1 AI + Semiconductors: A Mutual Dependence

• AI drives demand: Data‑center GPU and accelerator demand is the single largest growth engine for semiconductors up to 2030 (chart shown in slides).
• Semiconductor tech evolution: AI is pushing logic from FinFET → GAA → CFET, DRAM from 6F² → 4F², and NAND to multi‑tier 3D stacks. These three streams (logic, DRAM, NAND) account for >75 % of global silicon output.

2.2 Lam Research’s Market Position

• Lam is the second‑largest wafer‑fab equipment supplier globally (after ASML), providing ~20 % of worldwide fab equipment.
• Core technologies: deposition and etch; essential for increasingly complex 3‑D structures.

2.3 The “Complexity Explosion”

• Moore’s Law (transistor density doubling ~every 18 months) is paralleled by “Lam’s Law” – the number of process‑tool recipes also doubles every 18 months, reaching 10²¹ possible recipes on a single advanced etch tool.
• Human cognition alone cannot manage this combinatorial space; AI‑driven digital twins and machine‑learning optimisation are required to design, simulate, and operate equipment efficiently.

2.4 Digital‑Twin Stack (Semiverse Solutions)

Level	Purpose	Example
Equipment‑scale digital twin	Virtual design, pre‑delivery testing, remote maintenance	Full CAD model of a new etcher, virtual plug‑in of service scenarios
Subsystem (reactor) twin	Fluid, plasma, gas‑flow modelling before hardware is built	CFD/Plasma simulations to optimise reactor geometry
Feature‑scale twin	Process recipe development at wafer‑level	Predictive models linking gas chemistry to etch depth/selectivity
Fab‑scale twin	End‑to‑end fab throughput, yield forecasts	Integrated simulation of tool uptime, maintenance schedules, and product flow

• These twins accelerate equipment R&D, reduce physical prototyping cycles, and enable rapid deployment of next‑gen tools for AI workloads.

2.5 Global Talent Development Strategy

• Commitment (2023 US‑India joint announcement): Train 60 000 engineers in semiconductor disciplines over 10 years.
• Virtual‑lab approach: Deploy Lam’s proprietary simulation software to 80 Indian universities (plus institutions worldwide). Benefits:
  • Works on standard laptops – no need for multi‑million‑dollar fabs.
  • Safe, cost‑effective, and accessible to students in regions lacking physical labs.
• Progress to date (as of 2026):
  • 65 universities initially expressed interest; pilot launched at IISc Bangalore.
  • 14 faculty trained to become program “train‑the‑trainer”.
  • ~2 000 software licences deployed in the most recent semester; enrollment of ~570 students across 13 institutes (spring 2024).
  • Six semesters completed; cumulative enrolments now ≈ 4 000 per semester, on track to > 60 000 by 2034 (two years ahead of schedule).

2.6 Challenges & Next Steps

• Geographic imbalance: Most universities are in the South; expansion to the North is a priority.
• Hands‑on fab exposure: Virtual training is essential but must be complemented by physical fab training (e.g., INUP programs, dedicated training fabs).
• Industry‑academia alignment: Need for faculty fellowships (6–9 months industry placement) and industry‑sponsored capstone projects to keep curricula current.

2.7 Closing Remarks

• Re‑affirmed Lam’s belief that AI and semiconductors are inseparable; the company will continue to invest in workforce up‑skilling and digital‑twin R&D to keep pace with the AI‑driven demand surge.

3. Panel Discussion (Moderator: Paul Triolo)

3.1 Participants

Name	Role / Affiliation
Prof. Saurabh Chandorkar	Director, Centre for Nanoscience & Engineering, IISc Bangalore
David Fried	VP, Lam Research (Semiverse)
Mr. Rangesh Raghavan	Lam Research (India)
Mr. S Krishnan	METI Secretary (government)
Minister Shri Ashwini Vaishnaw	Minister of Electronics & IT (government)
(Absent)	Anand Ramamoorthy – Micron (personal emergency)

3.2 Themes Explored

1. Scope of the Talent Gap

   • David Fried: The “million‑person gap” is not a single job type. It spans field‑service engineers, process engineers, equipment engineers, metrology specialists, device engineers, reliability analysts, simulation experts, and more. The gap is breadth‑centric rather than skill‑centric.
   • Emphasis on deep industry understanding (what we produce, why it matters) over isolated technical tricks.

2. Academic Foundations & Physical Training

   • Prof. Chandorkar: IISc’s academic fab ranks among the world’s top‑3, but most Indian universities lack such facilities.
   • The Semiverse virtual platform has filled an important gap, yet hands‑on fab exposure remains essential.
   • IISc is establishing a training fab (INUP) to provide practical, tool‑level experience for students from across India.

3. Government Role (ISM 2.0)

   • Krishnan (METI): ISM 2.0 will broaden the original mission by adding skill‑building, supply‑chain integration, and manufacturing to its portfolio.
   • He called for policy support for faculty fellowships, industry‑university joint labs, and incentives for private‑sector training programmes.

4. Industry‑Academia Collaboration Models

   • David Fried: The train‑the‑trainer model (faculty workshops, software licences) works; the next step is co‑funded research projects and student‑industry internships.
   • Raghavan: Lam’s software distribution is a catalyst; similar models could be adopted by other OEMs (e.g., ASML) to broaden impact.

5. Strategic Recommendations

   Recommendation	Proponent
   Focus on “talent” instead of “skill” – develop a holistic understanding of the semiconductor value chain.	David Fried
   Create faculty‑industry fellowships – 6‑9 month industry placements for professors.	David Fried
   Scale hands‑on training fabs across regions – replicate INUP model in the North, East, and West.	Prof. Chandorkar
   Standardise industry‑relevant curricula – include modules on SPC, pressure‑gauge handling, PNID systems.	Paul Triolo (moderator)
   Encourage PhD projects aligned with fab‑scale challenges – e.g., AI‑driven process optimisation.	Panel (general consensus)

3.3 Audience Q&A Highlights

Questioner	Core Question	Key Answer(s)
Arish Kumar (CSTV)	How to develop a wafer‑development/skilling program for the solar industry?	Raghavan noted ongoing poly‑silicon wafer initiatives by a major Indian firm, and advocated a tri‑partite model (industry‑academia‑government) similar to the semiconductor effort.
Attendee (young‑career focus)	What first step should a young person take to enter the semiconductor market?	Emphasised problem‑solving, critical thinking, and a broad foundation in physics/chemistry/materials, discouraging early specialization on a single “skill”.
Audience Member (optimization query)	How does AI‑based optimisation differ between R&D (small data) and manufacturing (big data)?	Fried clarified: Optimization works best with abundant data (fab‑scale); in R&D, machine‑learning must be combined with physics‑based models because data is scarce.
General audience	What is the role of PhDs in the emerging fab ecosystem?	Panelists agreed PhDs bring resilience and a culture of iterative failure‑learning that is crucial for new fabs; they should be encouraged to pursue industry‑relevant research and short‑term industry stints.
Unidentified speaker	“Optimization policy” – request for more detail on AI‑optimisation for semiconductor processes.	Fried reiterated that tool‑specific AI (e.g., recipe recommendation) must be matched to the data regime; big‑data manufacturing contexts benefit most.

3.4 Closing Remarks

• Minister Ashwini Vaishnaw (brief words, not fully captured) thanked the participants and reiterated the Government’s commitment to support ISM 2.0, emphasizing that industry, academia, and the state must co‑create the talent pipeline.
• Paul Triolo thanked the panel, announced the next session, and invited a photo‑op with the speakers.

Key Takeaways

• AI is the dominant demand driver for semiconductors; the resulting technology roadmap (FinFET → GAA/CFET, DRAM 6F² → 4F², stacked NAND) requires ever‑more complex equipment and process recipes.
• Lam Research’s “Semiverse” virtual‑twin platform has become the central up‑skilling engine, already reaching 80 + Indian universities and on track to train > 60 000 engineers by 2034.
• The million‑person talent gap spans design, equipment, process, metrology, reliability, and service – a broad, ecosystem‑wide capability is needed rather than isolated “skill” training.
• Physical fab exposure remains essential; IISc’s training fab (INUP) and the proposed regional training fabs are critical to complement virtual learning.
• Policy recommendations for ISM 2.0: fund faculty‑industry fellowships, incentivise industry‑sponsored capstone projects, and create standardised curricula covering SPC, PNID, and equipment maintenance.
• Collaboration momentum: Lam Research’s leadership has spurred competitors and partners (e.g., ASML) to launch similar talent programmes, indicating a collective industry commitment.
• For aspiring entrants, focus on problem‑solving, critical thinking, and a solid grounding in physical sciences; avoid premature hyper‑specialisation.
• AI‑based optimisation is most effective in big‑data manufacturing environments, while R&D optimisation must blend physics‑based models with limited data.
• The Government’s role is to provide strategic funding, regulatory support, and coordination to ensure the holistic workforce ecosystem can meet the projected $100 bn domestic semiconductor market by 2030.

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Prepared from the verbatim transcript of the session “Shaping the Semiconductor Workforce in the Age of AI” recorded at the AI Conference, Delhi (2026). All speaker attributions have been reconciled with the supplied speaker list; where the transcript was ambiguous, the nearest logical attribution is used and flagged as [speaker uncertain]. Unclear utterances are marked [unclear].

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